ECET 230

  • ECET 230 Week 1 Homework Assignment

    ECET 230 Week 1 Homework Assignment

    ECET 230 Homework Assignment 1 1. Develop the Boolean equation for the circuit shown below 2. Determine the output Y in Problem 1 for the input values shown below 3. Redraw the circuit in Problem 1 using only 2-input NAND gates 4.Develop the Boolean...

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  • ECET 230 Week 2 Homework Assignment

    ECET 230 Week 2 Homework Assignment

    ECET 230 Homework Assignment 2 1. When a HIGH is on the output of the decoding circuit below, what is the binary code appearing on the inputs? 2. Write the Boolean equations for each of the following codes if an active-LOW decoder output is...

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  • ECET 230 Week 2 iLab Decoders and Multiplexers

    ECET 230 Week 2 iLab Decoders and Multiplexers

    ECET230 Week 2 iLab Decoders and Multiplexers Objectives: Discover the operation of 7-segment displays, BCD-to-7-semgment decoders, multiplexers and demultiplexers.  Demonstrate the simulation of a discrete DEMUX and decode operation with...

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  • ECET 230 Week 3 Homework Assignment

    ECET 230 Week 3 Homework Assignment

    ECET 230 Homework Assignment 3 1.Determine the decimal value of each of the following unsigned binary numbers: 2.Determine the decimal value of each of the following signed binary number displayed in the 2’s complement...

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  • ECET 230 Week 4 Homework Assignment

    ECET 230 Week 4 Homework Assignment

    ECET 230 Homework Assignment 4 1. Sketch the Q output for the waveforms shown below applied to an active-LOW S-R latch. Assume that Q starts LOW. 2. Sketch the Q output for the waveforms shown. Assume that Q starts LOW. 3. Sketch the Q output for...

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  • ECET 230 Week 4 iLab Introduction to Flip-Flops

    ECET 230 Week 4 iLab Introduction to Flip-Flops

    ECET230 Week 4 iLab Introduction to Flip-Flops Objectives:  Simulate an edge-triggered D flip-flop.  Test a 74LS74 D flip-flop and compare against predictions.  Describe and simulate edge-triggered D and J-K flip-flops with VHDL...

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  • ECET 230 Week 5 Homework Assignment

    ECET 230 Week 5 Homework Assignment

    ECET 230 Homework Assignment 5 1.Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the circuit below. Attach the .vhd and simulation files. 2.What is the output frequency of Q1 in the circuit shown...

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  • ECET 230 Week 6 Homework Assignment

    ECET 230 Week 6 Homework Assignment

    ECET 230 Homework Assignment 6 1.The group of bits 10110101 is serially shifted (right-most bit first) into an 8-bit shift register with an initial state of 11100100. After two clock pulses, the register contains:(a) 01011110 (b) 10110101 (c) 01111001...

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  • ECET 230 Week 7 Homework Assignment

    ECET 230 Week 7 Homework Assignment

    ECET 230 Homework Assignment 7 1. Is the state machine below a Moore machine or a Mealy machine? Explain your rationale. 3. Using the state diagram in Figure 10.44 on page 663 of the Dueck textbook, briefly explain the operation of the circuit shown...

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