# (TCO-4) A flip-flop input that only takes effect on a clock edge is called

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1. (TCO-4) A flip-flop input that only takes effect on a clock edge is called
2. (TCO 5) Which of the following is a definition of counter modulus?
3. TCOs 1 and 4) A VHDL design file includes the following statement: IF (CLOCK’EVENT and CLOCK = ‘0’) THEN. Which edge(s) of the clock is/are active?
4. (TCO 5) Many clocks and watches use a 32.768 kHz input signal. What is the modulus of the counter required to produce a 1 pulse/second output?
5. (TCO 5) A MOD 8 up-counter is holding the count 101 (base-2). What will the count be after seven clock pulses?
6. (TCO 5) What is the minimum number of flip-flops required for a counter that produces a 125 kHz output from a 10 MHz input? Show how you determine your answer.
7. (TCOs 1 and 5) Develop the VHDL Architecture for a MOD-10 binary up-counter. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.
8. (TCOs 1 and 4) Write the VHDL PROCESS statements for a D flip-flop with asynchronous active-LOW clear, synchronous active-LOW preset, and responsive to a falling edge clock. Use D for the input, Q and for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type.
9. (TCO-4) A flip-flop input that affects the output independent of a clock edge is called
10. (TCO 5) Which of the following is a definition of counter modulus?
11. (TCOs 1 and 4) The following is a portion of the ARCHITECTURE file for a flip-flop. When does the flip-flop change state? (Outputs are Q and NOT Q)
PROCESS (PRE, CLR, CLK)
BEGIN
IF (CLK’EVENT AND CLK = ‘0’) THEN
Q <= NOT Q;
12. (TCO 5) Many clocks and watches use a 32.768 kHz input signal. What is the modulus of the counter required to produce a 1 pulse/second output?
13. (TCO 5) A 4-bit binary up/down counter is set to zero. If the DOWN mode is selected and a clock pulse applied, the counter value will be _____.
14. (TCO 5) What is the minimum number of flip-flops required for a counter that produces a 125 kHz output from a 10 MHz input? Show how you determine your answer.
15. (TCOs 1 and 5) Develop the VHDL Architecture for a MOD-10 binary down-counter that counts down from 15. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.
16. (TCOs 1 and 4) Write the VHDL PROCESS statements for a D flip-flop with synchronous active-LOW clear, synchronous active-LOW preset, and responsive to a rising edge clock. Use D for the input, Q for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type.
17. (TCO-4) A J-K flip-flop has Q = 1. The output does not change on the next activating clock edge when _____.
18. (TCO 5) What is the MOD number for a binary counter with 4 bits?
19. (TCOs 1 and 4) A VHDL design file includes the following statement: IF (CLOCK’EVENT and CLOCK = ‘0’) THEN. Which edge(s) of the clock is/are active?
20. (TCO 5) A production plant has a requirement for a counter that will count 4,000 items before recycling and starting over. How many flip-flops are required?
21. (TCO 5) What is the highest count for a MOD-13 up-counter that begins at zero?
22. (TCO 5) Determine the period for the most significant bit for a counter circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. The counter is not truncated.
23. (TCOs 1 and 5) Develop the VHDL Architecture for a binary up-counter that inputs a clock of 876 kHz and outputs a signal of 12 kHz. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.
24. (TCOs 1 and 4) Write the VHDL PROCESS statements for a D flip-flop with asynchronous active-LOW clear, synchronous active-LOW preset, and responsive to a falling edge clock. Use D for the input, Q and for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type.
25. (TCO-4) A flip-flop input that only takes effect on a clock edge is called
26. (TCO 5) Which of the following is a definition of counter modulus?
27. (TCOs 1 and 4) The following is a portion of the ARCHITECTURE file for a flip-flop. When does the flip-flop change state? (Outputs are Q and NOT Q)
PROCESS (PRE, CLR, CLK)
BEGIN
IF (CLK’EVENT AND CLK = ‘0’) THEN
Q <= NOT Q;
28. (TCO 5) A MOD 5 and a MOD 20 counter are cascaded. What is the output frequency if the input frequency is 60 MHz?
29. (TCO 5) A MOD 15 up-counter is holding the count 1010 (base-2). What will the count be after seven clock pulses?
30. (TCO 5) What is the minimum number of flip-flops required for a counter that produces a 125 kHz output from a 10 MHz input? Show how you determine your answer.
31. (TCOs 1 and 5) Develop the VHDL Architecture for a MOD-10 binary down-counter. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.
32. (TCOs 1 and 4) Write the VHDL architecture file for a J-K flip-flop that toggles on each falling clock edge. Use J and K for the inputs, Q for the output, and CLK for the clock. All signals are BIT type.
33. (TCO-4) A flip-flop input that affects the output independent of a clock edge is called
34. (TCO 5) What is the MOD number of a single toggling flip-flop?
35. (TCOs 1 and 4) A VHDL design file includes the following statement: IF (CLOCK’EVENT and CLOCK = ‘0’) THEN. Which edge(s) of the clock is/are active?
36. (TCO 5) Many clocks and watches use a 32.768 kHz input signal. What is the modulus of the counter required to produce a 1 pulse/second output?
37. (TCO 5) What is the highest count for a MOD-13 up-counter that begins at zero?
38. (TCO 5) Determine the period for the most significant bit for a counter circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. The counter is not truncated.
39. (TCOs 1 and 5) Develop the VHDL Architecture for a binary up-counter that inputs a clock of 1.2 MHz and outputs a signal of 960 Hz. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.
40. (TCOs 1 and 4) Write the VHDL PROCESS statements for a D flip-flop with synchronous active-LOW clear, synchronous active-LOW preset, and responsive to a rising edge clock. Use D for the input, Q for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type.
41. (TCO-4) A flip-flop input that affects the output independent of a clock edge is called
42. (TCO 5) How many flip-flops are required to build a MOD 100 counter?
43. (TCOs 1 and 4) The following is a portion of the ARCHITECTURE file for a flip-flop. When does the flip-flop change state? (Outputs are Q and NOT Q)
PROCESS (PRE, CLR, CLK)
BEGIN
IF (CLK’EVENT AND CLK = ‘0’) THEN
Q <= NOT Q;
44. (TCO 5) Determine the output frequency for a counter circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz.
45. (TCO 5) A MOD 15 up-counter is holding the count 1010 (base-2). What will the count be after seven clock pulses?
46. (TCO 5) Two binary up-counters are cascaded (the output of the first feeds the input of the second). If the first counter is a MOD 10 counter and the input frequency is 4.5 MHz, what MOD number is required for the second counter to produce an output of 5 kHz?
47. (TCOs 1 and 5) Develop the VHDL Architecture for a MOD-10 binary down-counter that counts down from 15. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.
48. (TCOs 1 and 4) Write the VHDL PROCESS statements for a D flip-flop with asynchronous active-LOW clear, synchronous active-LOW preset, and responsive to a falling edge clock. Use D for the input, Q and for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type.
49. (TCO-4) A flip-flop input that only takes effect on a clock edge is called
50. (TCO 5) What is the MOD number for a binary counter with 4 bits?
51. (TCOs 1 and 4) A VHDL design file includes the following statement: IF (CLOCK’EVENT and CLOCK = ‘0’) THEN. Which edge(s) of the clock is/are active?
52. (TCO 5) A production plant has a requirement for a counter that will count 4,000 items before recycling and starting over. How many flip-flops are required?
53. (TCO 5) A MOD 8 up-counter is holding the count 101 (base-2). What will the count be after seven clock pulses?
54. (TCO 5) A clock signal with a period of 50 µs in applied to a counter. What is the modulus of the counter if the output frequency is 400 Hz?
55. (TCOs 1 and 5) Develop the VHDL Architecture for a binary up-counter that inputs a clock of 876 kHz and outputs a signal of 12 kHz. Use Q as the outputs and CLK as the clock input. All signals are INTEGER type.
56. (TCOs 1 and 4) Write the VHDL architecture file for a D flip-flop that toggles on each rising clock edge. Use D for the input, Q for the output, and CLK for the clock. All signals are BIT type.